The present invention relates to shifting the phase of a signal, and more particularly to a digital phase shifter for shifting the phase of a clock signal by a programmable number of degrees.
A typical method of shifting the phase of a signal is to use a phase-locked loop (PLL) with a variable phase shifter. The signal, such as a clock signal, is input to a phase detector where it is compared with the output of a VCO. The difference in phase is converted to a control voltage that is used to control the phase of the VCO. The variable phase shifter is inserted in the feedback loop between the output of the VCO and the input to the phase detector so that the signal output from the VCO has the desired phase relationship to the signal input to the PLL. Other analog techniques use tapped delay lines, with the taps coupled to a multiplexer to select the appropriate tap for output as the phase shifted signal.
A prior digital method of shifting the phase of a signal uses a heterodyne concept, as disclosed in U.S. Pat. No. 4,677,395 issued Jun. 30, 1987 to Daniel G. Baker entitled "Digital Phase Shifter", incorporated herein by reference. A continuous wave (cw) signal is mixed with a VCO signal which is an integer multiple of a difference frequency. The difference frequency is phase-locked and the VCO signal is divided into N increments by a counter. The count is compared with a desired phase shift value that is added to the difference frequency. The phase shifted difference frequency is then converted up to produce the phase shifted cw signal.
What is desired is a digital phase shifter that is more accurate than the prior analog phase shifters while avoiding the complexity of the digital heterodyne technique.